I. Field of the Invention
The invention relates to integrated circuits in general, and in particular, to techniques and devices for reducing electrical noise in VSLI chips.
II. Prior Art
The rapid advance in circuit technology has made it possible for entire systems and subsystems, such as microprocessors, etc., to be implemented on a single chip. A conventional VSLI chip includes a common substrate upon which a multitude of interconnected digital and analog electrical circuits are mounted. Usually, the digital circuits occupy anywhere from 80% to 90% of the chip. The analog circuit occupies the remaining portion of the chip. The analog circuit is usually positioned at the periphery of the chip and interfaces the digital circuitry with the external world. The advantage of combining digital and analog circuits on a single VLSI chip includes lower cost, reliability, performance enhancements, card area reduction, power dissipation reduction, stability design from system to system, etc. Still other reasons and advantages for integrating digital and analog circuits on a common substrate are set forth in the articles "The Design of High-Performance Analog Circuits on Digital CMOS Chips," Eric A. Vittoz, IEEE Journal of Solid State Circuits (ISCC), Vol. SC-20, No. 3, June, 1985 and "State of the Art and Future Prospect for Analogue Signal Processing-A Tutorial," Temes, Gabor C. et al, IEEE Proceedings 1988 ISCAS, pages 1655-1660.
A major problem which limits the use and acceptance of mixed circuit VLSI chips is noise. Digital circuits are inherently noisy. The faster the circuits, the noisier they become. On the other hand, analog circuits are predominately quiet. Digital noise generation is due, in part, to the rapid rate at which the digital components are switched. When digital and analog functions share the same chip, the noise generated by the digital circuits is coupled into the analog circuits. The coupled noise may cause errors in the low amplitude sensitive analog circuits.
The noise problem in digital/analog chips is a complex, phenomenon which is explained in FIGS. 1A through 4.
FIG. 1A shows a typical logic circuit output stage in which PFET 10 is connected to NFET 12. The P-channel FET (PFET) is connected with its source node connected to the positive power supply, (VDD) and its drain node is connected to the output (OUT) node. The N-channel FET has its source node connected to ground (GND), and its drain node connected to the output (OUT) node. The gate node of both devices is common and tied to input node (IN). The bulk region of each device (not shown) is tied to the appropriate power rail (VDD or GND) that provides for device biasing during circuits operation. For the P-channel device, the bulk region is the N-well diffusion (not shown). The N-channel bulk is the substrate, P-type silicon. It should be noted that for a P-well process, the N-channel bulk region would be a P-well and the P-channel bulk, the N-type substrate.
FIG. 1B shows a cross section of the structure shown in FIG. 1A. The structure includes an N-well in which the P-channel FET is formed, a well contact N+, a substrate contact P+ and the N-channel FET. The N-channel FET N+ source and the (P-Sub) substrate are tied via metal conductor 14 to pin or node C-GND. The node or pin C-GND is the chip ground. The output pin or output node (OUT) is connected by metal conductor 16 to the drain electrodes of P-channel and N-channel device while input node (IN) is coupled by a metal conductor 18 to the gate electrodes of the P and N-channel device. The power supply node on pin C-VDD is connected by a metal conductor 20 to the P+ source and the N-well of the P-channel FET. To minimize the risk of latch-up, substrate and well contacts are located in close proximity to the source contacts of the N-channel and the P-channel FETs. The showing in FIG. 1B represents a CMOS structure in which the close proximity of the source and bulk contacts minimizes the bulk resistance between the emitter and base of the parasitic bipolar transistors in the structure. It should be noted that "pin" and nodes are used synonymously.
FIG. 2 is a schematic showing a plurality of N-channel devices fabricated on a common P-substrate (P-sub). The figure also shows parasitic circuit components which are formed between the various substrate and device contacts when the chip is in operation. The layout in FIG. 2 is fairly typical and shows the ground current components which contribute to the noise problem of a mixed signal VLSI chip. The chip pin (C-GND) is coupled by metal conductor 22 to the card ground (GND). As a result of this interconnection, a package lead inductance (L1) is between the card ground and the chip ground (C-GND). Also, RCD is the substrate contact resistance formed between substrate (node ND) and the metal at C-GND1 while (CJD) is the P-N junction capacitance formed between the P-sub and the N+ diffusion. Currents I1, I2, I3 through IN are currents which flow into the chip node (C-GND) as a result of the N-channel devices discharging the capacitance load on the output node substrate. The respective arrows indicate direction of current flow.
When the chip is in operation, the current for each digital circuit is summed at chip ground node, C-GND, and flows through the package leads 22 to the card ground GND. The value of L1 represents the effective inductance of the package leads. The value of RCD represents the contact resistance of the substrate contact along with a small amount of resistance caused by the substrate resistivity in the region between the substrate contact and the N-channel diffusions. The value of CJD is the PN junction capacitance of the substrate to diffusion capacitance. The node in the substrate region near the N-channel FET is represented by the symbol ND.
For typical large VLSI chips, there can be several thousand digital circuits that simultaneously switch. Thus, ID which is the summation of current from all FETs on the chip can be very large. Stated mathematically, ##EQU1## where I represents current, j and n represent digits.
In addition, due to the fast switching rate of present day VLSI circuitry, the rate of change of the current, di/dt can be very large. When this current transient is forced through L1, the voltage of the chip ground (C-GND) caused by the inductive drop L1.times.di/dt can be significant (in the 1.5 volts-2.5 volts range for some chips). The change in voltage at (C-GND) is often referred to as ground bounce. Due to the presence of RCD and CJD, the substrate node ND will also experience the ground bounce occurring at the C-GND ground. Stated another way, the instantaneous change in voltage occurring at C-GND is coupled through the substrate to the region ending near the N-channel device. As will be described subsequently, this disturbance (ground bounce) or electrical noise transmitted through the substrate to the analog section of the circuit (to be described and shown subsequently).
Turning now to FIG. 3, a typical cross section for the digital and analog portion of a mix chip is shown. The right half of the chip represents the analog section while the left half represents the digital section. The digital cross section of the chip has been described in relationship to FIGS. 1B and 2 above and will not be repeated here. The analog portion of the chip includes an analog substrate contact (P+), an analog ground diffusion node (N+) and an output diffusion node (N+). RCA is the resistance of the analog substrate contact from (C-GNDA) to the NA node. Capacitor CJAG interconnects node NA to the analog ground node (C-GNDA). Capacitor CJA (the P-N junction capacitance) interconnects node NA to the diffusion node (N+). Since the substrate (P-SUB) is common for the analog and digital devices, the digital node ND and analog node NA are connected by a substrate resistance Rsub. Rsub is part of a conductive path interconnecting the digital node ND to the analog node NA. Therefore, any substrate bounce at ND is coupled through R-SUB to NA and is subsequently coupled to the N+ diffusions through the unavoidable junction capacitance CJA.
FIG. 4 shows an equivalent circuit for the mixed circuit of FIG. 3. As discussed previously, any internal noise ground bounce which is experienced at node ND is coupled through R substrate (R-SUB) and presented to node X. Node X is the junction point for the output from amplifier A1 and an input to amplifier to A2. Amplifiers A1 and A2 are analog circuits on the chip. Also, V.sub.R represents a signal generator. The signal that is being processed through the analog circuit passes through amplifier A1 and appears at node X. V.sub.R is assumed to be an external signal source with a low output impedance. Since the output of the signal generator is low, it can be assumed that V.sub.r input is clamped to one leg of the two input amplifier A2. Most on chip CMOS amplifiers have relatively large output impedance. Therefore, noise coupled through the junction capacitors of amplifier A1 output stage will appear at X together with the ground bounce from node ND and amplified through amplifier A2. Thus, the circuit topology in FIG. 4 which is the typical mixed (digital and analog) topology, is plagued with noise at the input of amplifier A2.
It is believed that as VLSI geometry is continued to shrink, more circuits will be placed in a given chip area and the noise environment will become even less favorable to sensitive analog functions on the same chip. The decreasing device dimensions of scaled VLSI will also have an adverse effect on the analog functions. For example, the scaling impact will necessitate a power supply voltage reduction. For a given noise floor, the reduced power supply voltage limits the signal swing. The lower power supply voltage is required by the scaled digital (now 5 volts going to 3.3 volts) and will greatly reduce the theoretical upper limit of the signal-to-noise ratio. When combined with the increasing noise generated by the denser logic, a decreasing theoretical limit of signal-to-noise ratio gives rise to a double sided squeeze on the analog design. A more detailed discussion of the effect of the decreasing device dimensions on the sensitive analog circuit of a chip is set forth in Cato, K. et al, in an article entitled, "A 300 Megahertz Monolithic Video Current Driver for High Resolution CRT Applications," IEEE JSSC, August 1989, pp. 1110-1117.
The prior art has recognized the noise problem and has suggested corrective techniques. For example, in an article entitled, "Reduced Ground Bounce and Improved Latch-Up Suppression Through Substrate Condition," Gabara, Tadius, IEEE Journal of Solid State Circuits, Vol. 23, No. 5, October 1988 (pgs. 1224-1232), the package lead inductance is reduced by removing approximately half of the I/O bonding wire leads in the power network and connecting the power supply through the substrate. The technique as a noise suppressor is questionable in that the current in the substrate must still flow through the package lead frame inductance and this can result in considerable noise coupling into sensitive analog functions on the chip.
Another technique for reducing lead inductance is set forth in Peddler, D. J. "Interconnection and Packaging of Solid-State Circuits," IEEE JSSC, June 1989, pp. 698-703. In this technique, the flip chip bonding reduces the lead inductance. Flip chip bonding is where the chip is soldered directly to the package, greatly reducing the chip to package inductance, and somewhat reducing the lead frame inductance. Even though the flip chip bonding technique appears attractive, its drawbacks are that it is expensive and it only reduces package inductance but does not eliminate it. In order to utilize low-cost packaging and still achieve good noise immunity, new techniques are needed.